1. Technical Field
The present disclosure relates to a method for forming an insulated electric connection between the front surface and the rear surface of a substrate. This electric connection is currently designated in the art as a through silicon via or TSV.
2. Description of the Related Art
In some electronic devices, chips are stacked. This increases the functions carried out by this type of device, without increasing the occupied surface area. A large selection of technological platforms is available for this purpose.
In such devices, to connect the different chips, it can be provided to use known techniques of wire bonding or vias crossing the semiconductor substrate of the chips.
In addition to being able to be collectively formed in silicon wafers, vias have the advantage of improving the electric performance of devices.
A known via forming method is the following. Once the electronic components have been made in the semiconductor substrate (this substrate being possibly thinned down), through vias are formed. Openings are created in the rear surface of the substrate by dry etch or chemical etch. The walls of each of the openings are then insulated by deposition of a silicon oxide layer by a method of chemical vapor deposition (CVD) type. The openings are filled with copper, by the use of an electrolytic growth method. A through via is thus obtained. Since the vias are insulated after the electronic components have been formed, the silicon oxide deposition method is submitted to thermal stress. The insulator may not be formed at a temperature exceeding 200° C. In such conditions, the silicon oxide can only be deposited by a low-temperature CVD type method. The obtained insulator is of poor quality and is not conformal. It has a degraded electric performance.
Further, when the vias are formed from the rear surface, the alignment references with respect to the front surface are lost. To provide a sufficient insulation between vias, the distance separating them is increased. The via integration density is thus decreased.
To overcome these disadvantages, it may be provided to form the through vias before forming the electronic components in the substrate. The substrate is first etched to form a plurality of openings. A step of thermal oxidation of the opening walls is then carried out. This step, performed at approximately 1,000° C., provides an insulator of good conformality. A filling with polysilicon is then performed. However, this material is very resistive. A filling with a metal such as aluminum, tungsten, or copper cannot be performed since these metals tend to diffuse into the substrate through the insulator during the anneal steps to form the components.